The state of the art resistor memory device arrays requires an active device on a non-volatile memory element. In the case of a resistor memory device, such devices are either a one-resistor, one-transistor array, or a one-resistor, one-diode array, however, these arrays are not suitable for use in three-dimensional arrays for ultra high-density memory integration. The invention disclosed herein resolves this problem, as the memory cell of the invention may be incorporated into a large memory array, and does not require an active device. cl Summary of the Invention
A memory array layer for use in a 3D RRAM, formed on a silicon substrate having peripheral circuitry thereon, includes a first layer of silicon oxide, deposited and planarized; a bottom electrode formed of a material taken from the group of materials consisting of Pt, PtRhOx PtIrOx and TiN/Pt; a second oxide layer having a thickness of at least 1.5X that of the thickness of the bottom electrode, deposited and planarized to a level where at the bottom electrode is exposed; a layer of memory resistor material; a layer of Si3N4; a third oxide layer having a thickness of about 1.5X of that of the memory resistor material; CMPd to expose the memory resistor surface; a top electrode formed of a material taken from the group of materials consisting of Pt, PtRhOx PtIrOx and TiN/Pt; and a covering oxide layer. Multiple memory array layers may be formed on top of one another.
A method of programming a 3D RRAM in a single step includes selecting a memory cell to be written to; applying a high voltage programming pulse to a first related bit line; applying a low voltage programming pulse to a second related bit line; floating the associated word line; biasing all other word lines with half-programming pulse voltages; and biasing all non-selected bit lines to the ground potential.
A method of programming a 3D RRAM in a two-step operation includes selecting a memory cell to be written to; applying a low voltage programming pulse to a first memory resistor in the memory cell; applying a high voltage programming pulse to a second memory resistor in the memory cell; setting the selected word line to ground potential; biasing all other word lines are biased to 0.5 VP; biasing a first related bit line with a negative programming pulse, having a pulse amplitude of −VP; biasing a second related bit line with a positive programming pulse, having amplitude of +VP; and pulsing all non-selected memory resistors with a programming voltage of between 0VP and 0.5 VP.
The memory cell of the invention may be read by applying a small voltage to the word lines of the non-selected bits to enhance the line voltage difference between the first related bit line and the second related bit line; and applying a read voltage to the word line associated with the selected memory cell and detecting the voltage difference between the first related bit line and the second related bit line.
It is an object of the invention to provide a reliable resistive non-volatile suitable for three-dimensional structure ultra high-density memory array which does not require an active device.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.